1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming a semiconductor device.
2. Description of Related Art
Recently, dimensions of transistors have become smaller due to miniaturization of semiconductor elements. The dimensional reductions of the transistors will cause remarkable short channel effects of the transistors. As the dimensions of memory cells in dynamic random access memories (DRAMs) and the like are reduced, the channel lengths of transistors are also reduced, which may cause degradation of the performance of transistors. The deterioration in retention of memory cells or writing characteristics has been problematic.
In view of the above, recess (trench) field effect transistors (FETs), fin FETs, and the like have been developed. The recess (trench) FET has a structure in which a trench (also called a groove) is formed in a semiconductor substrate to obtain a channel having a three-dimensional structure. Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2005-064500, JP-A-2007-027753, and JP-A-2007-305827 disclose that the fin FET has a structure in which a fin is formed between trenches to obtain a channel having a three-dimensional structure.
The trench FET is formed by forming a trench in a semiconductor substrate and forming a gate electrode within the trench while a gate insulating film is interposed between the gate electrode and the semiconductor substrate. A channel of the trench FET has a three-dimensional structure. The fin FET is formed by forming a gate electrode over a gate insulting film so as to cross over a fin protruding from a bottom surface of the trenches formed in the semiconductor substrate. Consequently, the channel has a three-dimensional structure. In any case, it is possible to suppress the short channel effects because the gate length can be lengthened with respect to the channel width.
A study has been carried out to adopt buried gate transistors for selecting transistors included in memory cells in the DRAMs due to reduction in size of the memory cell. The buried gate transistor has a structure in which a gate electrode is buried in the semiconductor substrate.
The gate electrode of the buried gate transistor does not protrude from the surface of the substrate because the gate electrode (word line) is buried in the semiconductor substrate. Among wirings connected to memory cells, only bit lines are located over the semiconductor substrate. This will increase flexibility of layouts of capacitors, contact plugs, and the like, which are included in the memory cell and formed over the semiconductor substrate. This will reduce the difficulty of processing the capacitors, the contact plugs, and the like.
A transistor as shown in FIG. 18 has the channel of the three-dimensional structure described above. The transistor is formed as follows. An isolation region 101 and an active region 102 are formed in a surface portion of a semiconductor substrate 100. Trench portions 103 and 104 for a buried gate electrode are formed in the isolation region 101 and the active region 102, respectively. A fin portion 107 is a protrusion which is a part of the active region 102 between the trench portions 103. A saddle fin gate electrode 106 is formed by burying a conductive material in the trench portions 103 and 104 while a gate insulating film 105 is interposed between the saddle fin gate electrode 106 and the semiconductor substrate. That is, the saddle fin gate electrode 106 crosses over the fin portion 107. An upper surface 107a of the fin portion 107 is located to be higher than a bottom surface of the trench portion 103 and to be lower than an upper surface of the active region 102 (an upper surface of the semiconductor substrate 100). This is because the trench portion 104 in the active region 102 is shallower than the trench portion 103 formed in the isolation region 102. A source region 108a and a drain region 108b (impurity diffusion layers) are formed, by implanting ions, in two active regions 102 between which the gate electrode 106 is interposed.
However, widths of the trench portions 103 and 104 for the buried gate electrode become narrow due to the reduction in dimensions of the memory cell described above. Thus, widths of channel regions formed in the upper surface 107a and a side surface 107b of the fin portion 107 also become narrow in correspondence with the widths of the buried gate trench portions 103 and 104. Therefore, in some cases, it is difficult to sufficiently secure an ON current due to a short channel effect.